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Matrox Rapixo CXP is a new generation of frame grabbers, supporting version 2.0 of the CoaXPress® (CXP) digital interface standard for machine vision applications. The Matrox Rapixo CXP family supports data rates of either up to 6.25 Gbps (CXP-6) or up to 12.5 Gbps (CXP-12) per connection. The PCIe® host interface comfortably matches the maximum input bandwidth from the CXP links. The CXP links are accessed through high-density BNC connectors allowing for a homogenous interconnection with new cameras. Power-over-CoaXPress (PoCXP) support on each connection simplifies system configurations, combining the camera’s power interface with its command- and data-interface onto the same coaxial cable.
The Matrox Rapixo CXP family of frame grabbers feature one, two, or four connections for interfacing to independent cameras. Matrox Rapixo CXP Dual and Quad can also handle higher data rates through connection aggregation. The Matrox Rapixo CXP family possess sufficient onboard memory to buffer incoming image data in situations where the host computer is temporarily unable to accept data. The fanless design for select models ensures extended use without maintenance.
The Matrox Rapixo CXP Pro makes use of a field-programmable gate array (FPGA) device from the Xilinx Kintex® UltraScale™ family for not only integrating the controlling, formatting, and streaming logic of the various interfaces, but also allowing developers to incorporate Matrox Imaging- or user-developed custom image pre-processing operations to offload from the host computer. A variety of FPGA sizes are available for the Matrox Rapixo CXP Pro, providing a range of solutions tailored to a given application. Operations performed on-board are controlled through Matrox Imaging Library (MIL) application-development software. Within MIL, an existing FPGA configuration can be rearranged to perform a required sequence of operations without necessarily having to generate a new FPGA configuration. Using the Matrox FPGA Development Kit (FDK), developers generate their own FPGA configurations with custom operations written in C/C++.