Matrox FDK - HLS Design Flow Part 1
Explains how to validate HLS C code by simulating FPGA hardware in Visual Studio using HLS example PUs, as well as compiling HLS C code for hardware using Vivado HLS once the code is validated. Finally, packaging code for use with Vivado IP integrator is shown.
Matrox FDK - HLS Design Flow Part 2
Demonstrates the creation of a Vivado IP Integrator project, including integration of example PUs in an IP repository, the use of the block design interface and the generation of new FPGA firmware. The Rapixo board is then updated with the new firmware and example PUs are tested in hardware.
Matrox FDK - Creating a new project using Vivado IP Integrator
Explains how to create a new Vivado IP Integrator project, including the basics of block design, the address editor, Vivado Synthesis, Implementation and the generation of a firmware bitstream. Along the way, FDK building blocks, customization features and updating the Rapixo’s firmware are described.